Sun, Fujitsu take Sparc to 90 nanometers

Sun Microsystems Inc. and Fujitsu Microelectronics Inc. plan to reveal details about their new dual-core Sparc-based processors at the Microprocessor Forum conference in San Jose, California, this week.

Sun will disclose more details on its forthcoming UltraSparc IV processor, which will be the first UltraSparc chip designed to execute more than one set of instructions at the same time.

The UltraSparc IV will be built with two 1.2 GHz UltraSparc III cores and will be able to handle two threads simultaneously. However, Sun's road map calls for a significant increase in the number of threads UltraSparc chips can run over the next few years. The 8-core Niagara processor, expected in 2006, will be able to handle 32 threads, for example.

Sun's multithreaded approach to chip design dovetails with the multithreaded nature of the company's Solaris operating system, said Andy Ingram, Sun's vice president of marketing for the processor and network product groups. Because Sun has spent over a decade designing Solaris to handle multiple threads in SMP (symmetric multiprocessor) machines like its 106-processor Sun Fire 15K systems, Sun's Unix is well suited to the new multithreaded chips, he said.

"We've been working on the threading model of Solaris for 12 years, so we know we can run hundreds of threads," he said.

Java has also contributed to the UltraSparc IV's design, said Kevin Krewell, the general manager of Microsdesign Resources, the electronics industry analysis firm that hosts Microprocessor Forum. "Their work with Java has certainly inspired this because Java generates lots of threads and Solaris is well tuned to handle a lot of threads," he said.

Fujitsu Ltd. will unveil its Sparc64 VI processor at the show, the first of which will be a dual core 2.4GHz processor with 6M bytes of Level 2 cache. It will be built with a 90-nanometer (nm) process, which means circuit lines on these chips will be about one thousandth the thickness of a human hair. A nanometer is one billionth of a meter.

The Sparc64 VI will ship a few months later than previously expected, said Tom Donnelly, the product manager for Fujitsu's PrimePower servers. The first chip in the line is expected to ship in systems by early 2006, he said.

The chips have 690 million transistors and will also have a new "mainframe bus," designed to speed up communication between the processor and memory, Donnelly said.

The UltraSparc IV will have 16M bytes off-chip L2 cache and will be packaged in chip modules that can be easily added to UltraSparc III systems, according to Krewell. "It's a direct drop into the UltraSparc III, so they maintain the same infrastructure. It's a reasonably painless upgrade," he said.

The first UltraSparc IV will be based on 130-nm process technology, but its successor, like the Niagara processor, will be based on a 90-nm process, Sun's Ingram said.

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