IBM and Advanced Micro Devices (AMD) have jointly developed a new method for implementing strained silicon technology on both positive and negative transistors, the companies are expected to announce Monday.
The new manufacturing technique, which the companies are calling Dual Stress Liner, will help improve performance on chips from both companies starting early next year, the companies said in a statement. IBM and AMD claim they are the first to show simultaneous performance improvements on both positive and negative transistors using conventional materials. They are expected to provide more details on Monday at the International Electron Devices Meeting (IEDM) in San Francisco.
As it has become more difficult for chip companies to improve transistor performance by simply shrinking transistors, they have turned to alternative techniques to keep improving the performance of their products. Strained silicon is a technique in which a lattice pattern of silicon atoms is either stretched or compressed to improve the speed at which electrons flow through the silicon. Positive transistors run faster when they are compressed, and negative transistors run faster when they are stretched.
The companies believe that by using their strained silicon techniques on both positive and negative transistors they can improve transistor speed by as much as 24 percent, the statement said.
The strained silicon technology will be integrated into AMD's Opteron and Athlon 64 processors and IBM's Power processors in the first half of 2005.
In 2003, AMD and IBM signed an agreement to work on techniques for advanced transistor manufacturing. Joint development teams work at the premier manufacturing facilities of each company, in Dresden, Germany, and East Fishkill, New York, respectively. The companies recently extended that agreement to carry through 2008.
Researchers from both companies will present a paper outlining their technique at IEDM on Monday, and they will hold briefings and a news conference to provide further details.