As Intel moves in step with the rest of the chip industry toward the multicore design era, it is preparing to overhaul the memory bus architecture that has served it well for so many years, according to company executives and analysts.
Multicore processor designs are considered the solution to the performance scaling problem brought on by increased amounts of power leakage in modern chips. Transistors are now so small that increasing a chip's frequency, and therefore the amount of power it consumes, is not the simple exercise that kept companies like Intel going for many years.
However, in order to fully realize the performance gains provided by multiple processor cores, chip companies need to find a way to deliver enough data to the processor from the main memory to keep those cores as productive as possible.
Intel's current front-side system bus design should be able to keep as many as four cores satisfied, depending on the frequency of those cores, said Stephen Pawlowski, an Intel senior fellow, at a recent briefing on Intel's multicore strategy.
But Intel might not want to wait until quadcore processors are available in 2007 to start moving away from its front-side bus architecture, analysts said. The company can either adopt on-chip memory controllers to connect CPUs (central processing units) to memory or enhance its current bus design with additional logic to help feed data to the CPU cores, they said.
Under Intel's design, the front-side bus connects the CPU to the main memory in a system. A memory controller on the system's chipset is responsible for coordinating the data traffic as it passes from the memory to the CPU.
Some companies, such as Advanced Micro Devices, Sun Microsystems and IBM recently integrated the memory controller onto the chip. An integrated memory controller reduces system latency, or the amount of time it takes for data to move from one component to another.
Analysts have forecast that Intel will eventually have to move off the front-side bus design simply to keep up with the performance of these rival chips. The company's decision to accelerate the development of its multicore designs could bring that concept about sooner rather than later, said Nathan Brookwood, principal analyst with Insight 64 in Saratoga, California.
Intel plans to release dual-core chips in 2005 that are expected to keep the front-side bus architecture, Brookwood said. But its quadcore processors scheduled for introduction around 2007 will be the first to implement a common system interface across many of those chips, he said.
Earlier this year, the company disclosed plans to implement a common platform between its Xeon and Itanium chips, with the goal of allowing server vendors to build systems around either chip for the same cost. Since it will have to make changes to the system logic around both processors, this would be an ideal time for Intel to build support for an integrated memory controller into the Xeon and Itanium lines, Brookwood said. The company could then extend this to the desktop and notebook product lines, he said.
The integrated controller would help Intel boost the performance of memory-intensive server applications, and help feed the multiple cores scheduled for the Xeon and Itanium processors of that generation. In fact, the Itanium processor of 2007 could have as many as eight cores, according to sources.
The other option for multicore designs would allow Intel to keep its front-side bus architecture by adding features to its processors known as arbitration units, said Dean McCarron, principal analyst with Mercury Research in Cave Creek, Arizona. Arbitration units help processors share resources such as access to memory or I/O, he said.
Many companies already do this in multiprocessor servers, McCarron said. Many servers with eight or more processors are actually organized around four-processor groups, he said. It wouldn't be a huge challenge for Intel to organize the same type of architecture in a processor with four or more cores, he said.
Intel has traditionally resisted changing its front-side bus architecture. An integrated memory controller can only work with the memory standard for which it was designed. With memory standards changing every 18 months or so, this means that companies have to tweak their chips in order to enable transitions such as the switch from DDR (double data rate) memory to DDR2 memory, McCarron said.
Also, Intel is a little gun-shy about integrated memory controllers after the poor results of its last design with an integrated memory controller, the analysts said. The Timna processor for PCs featured an integrated memory controller, but it was locked into Rambus Inc.'s RDRAM (Rambus dynamic RAM) memory technology, which was too expensive for most users. The chip never saw the light of day, partly because RDRAM never entered the mainstream and partly because Timna's chipset was delayed due to several manufacturing flaws.
But integrated memory controllers make a great deal of sense in the server world, said Kevin Krewell, editor in chief of the Microprocessor Report in San Jose, California. Many server applications, especially in the low-end server category where Intel is especially strong, handle memory-intensive tasks, he said.
Also, server designers are more conservative about adopting new memory standards than their PC counterparts, Krewell said. This means Intel would not have to tweak its server processors as often.
Intel declined to elaborate this week on the ability of its multicore designs to continue to rely on its front-side bus architecture. But just as the company has overhauled its road maps this year to move away from frequency-based designs, Intel will probably have to get off its front-side bus as the multicore era looms.