Engineers from Sun Microsystems will reveal the first technical details on the company's eight-core microprocessor, code-named Niagara, at the Hot Chips symposium on high-performance processors being held this August at Stanford University, according to an abstract of their discussion submitted to the Hot Chips show organizers.
An abstract of the talk obtained by the IDG News Service sheds some light onto the technical direction Sun is taking with Niagara, and how exactly Sun expects to improve the processing power of the chip while at the same time using a relatively low clock speed.
Niagara will have eight processor cores, each of which will be able to perform four independent processing tasks, or threads, at the same time, Sun has said. Niagara will then break these threads into binary instructions that will be executed six at a time, thanks to a "single scalar 6 stage pipeline," the abstract states.
The abstract appears to describe a low-power processor that will run at a relatively low frequency -- perhaps in the 1GHz range -- and that will be optimized for Web-based services, said Kevin Krewell, the editor-in-chief of The Microprocessor Report. "There are lots of threads, and those threads can be used efficiently by the short pipeline," Krewell said.
Niagara's efficient use of power will come, in part, from the fact that it has only six pipeline stages - far fewer, for example, than Intel's latest Pentium processor, code-named Prescott, which contains 32 stages, Krewell said. "With the short pipeline stage, you're not wasting a lot of energy with lots of deep pipelining," he said.
From the details available, Niagara looks like it is being designed for Web service providers like Google, said Krewell. "Google's architecture might play well with this design with lots of processors in a dense package with relatively good power efficiency per processor," he said.
Texas Instruments Inc. recently began manufacturing the first Niagara chips, which are designed but not built by Sun, so Sun engineers will probably be getting their first look at Niagara around the time of the Hot Chips presentation, Krewell said.
Each of Niagara's processor cores will include a crypto co-processor, and each Niagara processor will have one floating point co-processor, as well as 3M bytes of L2 cache, the abstract says.
The fact that Niagara will have one crypto co-processor for each of its eight cores, means that it will do well when performing security processing, for example sending and receiving information using the Secure Sockets Layer (SSL) protocol, Krewell said.
"Cache coherence is maintained by the L2 by means of a novel directory scheme, " the abstract states. Niagara's on-chip memory controller can be used to access up to 32G bytes of memory using 4 channels of DDR2 (Double Data Rate) memory interface over 20G bits/second of memory bandwidth, it says.
Sun, which declined to comment on this story, expects to begin shipping systems based on Niagara in early 2006.
The abstract lists four Sun engineers, Poonacha Kongetira, Kunle Olukotun, Kathirgamar Aingaran, and James Laudon as its authors.
Sun's Niagara presentation is scheduled for August 24.