A storage technology that breaks Moore's Law

A new kind of flash memory technology with potentially greater capacity and durability, lower power requirements, and the same design as flash NAND is primed to challenge today's solid-state disk products.

US-based Nanochip said it has made breakthroughs in its array-based memory research that will enable it to deliver working prototypes to potential manufacturing partners next year. Three investors, including Intel Capital, recently put US$14 million into the company, which has been developing the technology since its founding in 1996.

It's a technology that doesn't depend on Moore's Law," says Gordon Knight, CEO of Nanochip. "This technology should go at least 10 generations."

Knight was alluding to the decades-long trend in which the number of transistors that can be placed on an integrated circuit roughly doubles every two years. Current thinking is that flash memory could hit its limit at around 32 to 45 nanometers. That describes the smallest possible width of a metal line on the circuit or the amount of space between that line and the next line. The capacity of an IC is restricted by the ability to "print" to a smaller and smaller two-dimensional plane, otherwise known as the lithography.

And that, according to Stefan Lai, is where Nanochip's technology shines. Moore's Law is driven by lithography," says Lai, a member of Nanochip's technical advisory board, as well as vice president of business development at Ovonyx and former vice president of Intel's flash memory group.

Array-based memory uses a grid of microscopic probes to read and write to a storage material. The storage area isn't defined by the lithography but by the movement of the probes. "If [Nanochip] can move the probes one-tenth the distance, for example, they can get 100 times the density with no change in the lithography," says Lai. "You don't have to buy all these new machines."

Lai said that in principle, Nanochip could develop the ability to move the probe a single atom at a time. The company said its current generation of probes has a radius smaller than 25nm, but it projects that eventually the probes could be shrunk to two or three nanometers apiece. That scale, said Knight will enable development in 10 to 12 years of a memory chip greater than 1TB. For a first generation, anticipated in 2010, Knight says he expects a small number of chips to be in excess of 100GB, but a more realistic number is "tens of gigabytes" per integrated circuit, a capacity comparable to the current generation of flash devices.

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